Designers of Integrated Circuit (IC) technology typically strive to provide IC devices that take up a minimum amount of space, and operate reliably at high speeds while consuming a minimum of power. Of increasing importance in IC design is the management of heat generated by device structures of an IC, namely transistors.
The amount of heat generated in a particular IC, or portion of an IC, is dependent at least in part on a number of transistors, the frequency (speed) at which they operate, and/or an amount of electrical energy consumed. This generated heat may cause a variety of operational and/or structural issues. A “hot” IC may operate at limited speed (Many authors have posited that for every 10 degrees in heat reduction, a typical IC will operate at a 2% higher operating frequency), may suffer from data and other reliability issues, and may consume more power than a device operating at lower temperatures. The IC may even fail functionally or physically.
Recently, ever-increasing consumer demand for improved IC performance has caused IC designers to look to multi-substrate IC devices in which a plurality of integral IC device layers (substrate layers in which transistors or other IC device structures are formed) are stacked and interconnected in a single die. By utilizing multi-substrate designs, an IC can be provided in a more compact arrangement and lengths of wire routes (electrical connections between IC devices structures such as transistors) can be reduced. Shorter wire lengths may improve operation speeds, reduce parasitic effects on circuit operation, and improve a designer's ability to meet timing requirements.
Because multi-substrate IC devices incorporate transistors arranged in proximity in both horizontal and vertical dimensions they may be more susceptible to the effects of heat. As such it may be difficult to remove heat from such devices by traditional methods.
Some single or multi-substrate ICs are formed with silicon-on-insulator (SOI) structures that include an insulating layer formed between different semiconductor substrate layers and/or IC die. These insulating may layers trap heat in the IC, which may exacerbate issues related to the presence of heat.
Many technologies have been developed to remove heat from an IC, for example heat sinks. One example of a heat sink is described in U.S. Pat. No. 4,807,018 to Cellai, which describes a metallic structure adapted to be thermally coupled with one or more exterior surfaces of an IC die or package to transfer heat from the IC into the surrounding environment. Heat sinks may be coupled to an IC on a PC board, or may be included within an IC package.
Other solutions to IC heat management utilize fluid to cool an IC. For example, U.S. Pat. No. 5,388,635 to Gruber et al., U.S. Pat. No. 4,894,709 to Phillips et al., U.S. Pat. No. 7,219,713 to Gelorme et al., U.S. Pat. No. 7,157,793 to Torkington, et al., and U.S. Pat. No. 5,210,440 to Long each describe devices adapted to be placed in contact with or in proximity to one or more surfaces of an IC to circulate fluid in order to cool the IC. Additional, approaches, such as described in U.S. Pat. No. 7,170,164 to Chen et al., describe the formation of trenches in a surface of an IC, and the circulation of fluid through the trenches to cool the device. Still other approaches describe the formation of micro-fluidic channels at a back surface of a semiconductor die to dissipate heat. Similarly, other approaches provide for the formation of micro-channels on a surface of a plurality of stacked and interconnected die, such as described in A Cool Innovation Stack Microprocessors, Tom Adams (Chip Scale Review, pp. 24-29, Jan. 2009, http://e-ditionsbyfry.com/Olive/AM3/CSR/Default,htm?href=CSR/2009/010/01).
Other solutions have also been proposed. For example, U.S. Pat. No. 6,389,582 to Valainis et al. describes a thermal driven placement system for the automated placement of components of an IC design based on a thermal model of the design. Similarly, U.S. Pat. Pub. No. 2009/0024969 to Chandra describes the creation of a thermal model of an IC design and modifying one or more thermal management systems based on the thermal model. A thermal model of an IC design may include designations of “hot spots”, or those portions of the IC that generate a relatively greater amount of heat than other regions or portions of the IC.
Still other approaches provide one or more metallic heat flow paths internal to an IC die itself to remove heat from the design. For example, U.S. Pat. No. 5,955,781 to Joshi et al, describes the formation of heat conductive metallic structures internal to an IC design to dissipate heat directly from hotter elements of the IC. Other approaches, such as described in U.S. Pat. Pub. 2008/0266787 to Gosset et al., describe the formation of micro-fluidic channels in metallization layers of a single substrate IC die. The channels are coupled to an extra-die fluidic cooling circulation driver.
While the above-mentioned approaches for IC temperature management may mitigate the effects of heat on IC device operation, there is a need for improvements in IC thermal management.